1/6 L6316 september 2004 this is preliminary information on a new product now in development. details are subject to change without notice. 1 features dual power supplies of +5v, 10% and -3v, 6% low power consumption; 980 mw @ 800mb/s (single head 100% write mode duty cycle, random pattern, iw = 40ma, max ovs). flip chip package.L6316 differential voltage bias / voltage sense architecture. current bias available programmable read input differential impedance. selectable read path bandwidth from 200 to >600 mhz (rmr=40 ? ). (parameter dependent on interconnect) selectable lf corner (1, 2.5, 3.5 or 5.5 mhz with rmr=40 ? ). noise figure of merit; 2.2 db (rmr=40 ? ) mr bias voltage programmable from 70 to 225 mv nom. (5 bits) (7.2ma max). mr bias current programmable from 0.65 to 7.2 ma nom. (5 bits) (225mv max). read input stage optimized for mr resistance from 20 to 70 ohm. programmable read voltage gain of 37, 40, 43, 46 db rmr = 40 ? , rload = 100 ? fully differential write driver: programmable overshoot amplitude (3bits) and duration (2bits). write current rise/fall time with custom head and interconnect model 140 ps at 40 ma (10% to 90%) (steady state to steady state) write current amplitude programmable (5 bits) 0 to 62 ma (0-pk). bi-directional 16-bit serial interface 2.5v and 3.3v cmos compatible. 2-pin (rxw and tfi), 2 bits mode selection (wake, entfi). all control signals are 2.5 & 3.3v cmos compatible. analog buffered head voltage abhv (gain of 5) automatic digital mr resistance measurement (7 bits). read head open detection, read head shorted detection. write head open or shorted to ground, writer to reader short, write data frequency too low detection. safedetect method for write fault detection. low vcc or vee supply & die over temperature detect, analog temperature measurement. fast write-to-read recovery 150ns (max) (same head). head-to-head switch in read mode 1.5us (nom). zero mr bias, very low power (43mw) idle mode with fast recovery to read mode 1.5us (nom). mr bias switching without overshoot for head protection. read-to-write switching 50ns (max) (same head). esd diodes for mr head protection 2 description the L6316 is a bicmos silicon germanium inte- grated circuit differential preamplifier. it is de- signed for use with four-terminal mr read and in- ductive write heads. in read mode, the device consists of a fully differential amplifier, offering; voltage or current bias, voltage-sense input, pro- grammable input impedance, low noise and high bandwidth. in write mode, it includes fast current switching differential write drivers, which support data rates up to 1200 mb/s. this preamplifier provides programmable read voltage or current bias and write current (5 bit dacs for the read bias and for the write current), fault detection circuitry and servo track writing fea- tures. read amplifier gain, low corner frequency, and write current wave shape are adjustable. the amplitude and duration of the overshoot are sepa- rately programmable through a 16-bit bi-direction- al serial interface (sen, sdata, and sclk). the device operates from +5v and -3v supplies. data brief 4-channel low power preamplifier rev. 1 fi gure 1. p ac k age table 1. order codes part number package L6316 flip chip flip chip
L6316 2/6 figure 2. preamplifier block diagram rxw predriver write drivers vcc (+5v) vgnd (0v) vee (-3v) wdx wdy flt sdata sclk sen tfi rdx rdy fault processor low supply detection, open/short heads, low write frequency, high temperature serial interface control head selection & mode control vref mr read input stages vmr, iw rw enable head select write dac read bias dac overshoot abhv, mr meas, temp meas temperature monitoring gain boost low pass filter 3v 3v L6316 high pass filter current/volt age bias rin dac hw0y hw0x hw1y hw1x hw3y hw3x hw2y hw2x hr0y hr0x hr1y hr1x hr3y hr3x hr2y hr2x
3/6 L6316 figure 3. flip chip pinout diagram - bumps down note: minimum pad pitch = 204 um and pad opening (octagonal) = 70 um bump sequence (see next table for coordinates) die dimensions: x = 2192 20 um y = 2686 20 um minimum distance between pads opening center to center: 204um wafer thickness: 500 20 um bump height: 90 15 um bump diameter: 120 15 um die center misalignment w.r.t original die center after cut: 38 um bump material if eutectic: 63% tin, 37% lead bump material if lead free: 96% tin, 3.5% silver, 0.5% copper note: vref pad can be left floating or grounded. do not connect it anywhere else. tf vee gnd vcc hr3y hr3x hw3y hw3x hw2x hw2y hw1y hw1x hw0x hw0y hr2y hr1y hr2x hr1x sden wdy sclk rdx rdy sdata rxw flt wdx vee gnd vref vcc hr0y hr0x 0,0
L6316 4/6 table 2. bump coordinates (bumps down, from center of die, dimensions in microns). note: vref pad can be left floating or grounded. do not connect it anywhere else. pin name x-coord (um) y-coord (um) pin name x-coord (um) y-coord (um) hr3y 471 1140 vref -278 -1140 hr3x 775 1140 gnd -482 -1140 hw3y 141.1 813.7 vee -686 -1140 hw3x 141.1 566.7 flt -890 -816 hw2x 141.1 362.7 rxw -890 -612 hw2y 141.1 115.7 sdata -890 -408 hr2y 686 102 rdy -890 -204 hr2x 890 252 rdx -890 0 hr1x 890 -252 sclk -890 204 hr1y 686 -102 wdx -890 408 hw1y 141.1 -115.7 wdy -890 612 hw1x 141.1 -362.7 sden -890 816 hw0x 141.1 -566.7 tfi -686 1140 hw0y 141.1 -813.7 vee -482 1140 hr0x 775 -1140 gnd -278 1140 hr0y 471 -1140 vcc -74 1140 vcc -74 -1140 - - -
5/6 L6316 table 3. revision history date revision description of changes september 2004 1 first issue in edocs dms.
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